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This course is designed to respond to this need of understanding and being able to program novel HPC architectures. Specifically, the course covers three types of HPC architectures – multi-core processors, GPU accelerators, and FPGA accelerators -, and the programming models and techniques used for them. High-performance computing has seen a lot of interesting advances in the last decade, in both architectures and programming models. In terms of architectures, we have seen massive parallelism and various kinds of accelerators appearing with the promise of TeraFLOPs of performance.
More and more application fields are tempted by the promise of many-fold performance gains, and willing to design and implement HPC solutions for their use-cases. Despite the enthusiasm, programming these novel HPC architectures is hard work. In fact, achieving the promised level of performance often requires suitable workloads, algorithm re-writing, multilayered parallelization, multi-grain concurrency, and aggressive optimization and tuning.
None of these challenges should be good reasons to give up, but reasons enough to get to know more about programming these novel HPC architectures, while understanding their strong points, their limitation, and ultimately their “down-to-Earth” performance.
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